1. Field of the Invention
The present invention relates to the field of a method of planarizing a semiconductor wafer by a local dry etching method, especially for planarizing in etching condition that nanotopography is prevented from occurring.
2. Description of the Related Art
In recent years, in order to planarize a silicon wafer, there has been used a local dry etching apparatus for locally etching the silicon wafer by activated species generated in plasma as disclosed in Japanese Laid-Open Patent No. 2000-223479. FIG. 1 shows a sectional view of a general example of such a local dry etching apparatus 200.
According to the local dry etching apparatus 200, sulfur hexafluoride (SF6) gas (or other compound gases of F) is subjected to electricity discharge by a plasma generator 100 to thereby produce F activated species and by injecting the F activated species gas G from a nozzle portion 101 to a surface Wa of a silicon wafer W on a chuck 120, etching is carried out locally at a portion of the surface Wa thicker than a reference thickness, or a relatively thick portion.
At this occasion, with regard to the relatively thick portion, moving speed of the chuck 120, that is, relative speed of the nozzle portion 101 is slowed to thereby prolong a time period of injecting the F activated species gas G and conversely, with regard to a thin portion, the relative speed of the nozzle portion 101 is speeded to thereby shorten the time period of injecting the F activated species gas G, thereby a total amount of etching (material removal) is adjusted for respective portions and the entire surface Wa of the silicon wafer W is planarized.
A rate of the material removal by the activated species gas G from the wafer W is referred to as etching rate E and is distributed in accordance with a distance from a central axis thereof as shown in FIG. 2. The distribution curve of the etching rate E is also referred to as etching profile.
Nanotopograghy is recesses and projections or surface height variation exists on the surface of a semiconductor wafer. A spatial wavelength of nanotopography falls in a range of 0.2 mm through 20 mm and a difference of height between a wave top and wave bottom (wave height) falls in a range of 1 through several hundreds nm. FIG. 3 shows an illustrative graph of nanotopography.
Multilayered wiring technology has been adopted for a semiconductor device manufacturing and in order to meet request from the wiring technology, there has been developed a chemical/mechanical composite polishing method referred to as CMP (Chemo-Mechanical Polishing). Although a surface of a semiconductor wafer can be planarized in very high accuracy by the CMP technology, there has been posed a new problem of a different and finer level of recesses and projections, that is, nanotopography. Nanotopography cannot be removed even by the CMP technology. As the yield of semiconductor device manufacturing is deteriorated by non-uniformity in thickness of the insulator layer of the wafer and the recesses and projections of the wafer surface cause non-uniformity, nanotopography has become a significant problem. As is a new problem, few technical documents, e.g. U.S. patent application Ser. No. 10/062494, deal in nanotopography.
Nanotopography is said to be caused by irregularity in each processing of semiconductor device manufacturing, e.g. non-uniformity in doping in a step of pulling up silicon crystal, lap mark, polish mark, slicing mark, etching mark etc.
The object of present invention is to prevent nanotopography from occurring in planarizing process of the wafers using local dry etching technology and further to remove nanotopography produced in the former processes of the wafers.
According to a first aspect of the present invention, there is provided a local dry etching method. The method includes the following steps: test etching a surface of a representative wafer sampled from a lot, wherein each wafer of said lot being sliced from the same ingot and initial data of recesses and projections of said representative wafer being known; measuring recesses and projections of said representative wafer after said test etching is executed; deriving an etching profile from said initial data and measured data in said measuring step; and etching respective wafer surfaces of said lot in condition calculated at least by using said etching profile.
According to a second aspect of the present invention, a local dry etching method according to the first aspect of the invention is provided. The method includes the following steps: calculating a scanning speed for planarizing said wafer based on an assumed pitch width and said etching profile and predicted nanotopography: and repeating the step of calculating a scanning speed by changing said assumed pitch width to a different value until nanotopography falls in an allowable range.
According to a third aspect of the invention, a local dry etching method according to the first aspect of the invention is provided, wherein: the step of test etching is executed by previously determined scanning speed along a test line on said representative wafer; and the step of measuring recesses and projections provides data of recesses and projections along a cross line in a direction perpendicular to said test line.
According to a fourth aspect of the invention, a local dry etching method according to the third aspect of the invention is provided. The method further includes the following steps: forming masking lines spaced apart from each other by a sufficient interval before the step of test etching a surface of a representative wafer; and removing said masking lines after the step of test etching a surface of a representative wafer; wherein measurement is executed by including regions protected by said masking lines in the step of measuring recesses and projections.
According to a fifth aspect of the invention, a local dry etching method according to the first aspect of the invention is provided, wherein: the step of test etching is executed by injecting an activated species gas from a nozzle stationary at one point on said representative wafer for a predetermined period of time; and the step of measuring recesses and projections provides data of recesses and projections on a line at least passing through said point.
According to a sixth aspect of the invention, a local dry etching method according to the fifth aspect of the invention is provided. The method further includes the following steps: forming a masking circle in a ring-like shape before the step of test etching a surface of a representative wafer; and removing said masking circle after the step of test etching a surface of a representative wafer; wherein measurement is executed by including region protected by said masking circle in the step of measuring recesses and projections.
According to a seventh aspect of the invention, a local dry etching method according to the first aspect of the invention is provided, wherein a stylus type surface roughness measuring apparatus is used in the step of measuring.
According to an eighth aspect of the invention, a local dry etching method according to the first aspect of the invention is provided, wherein an optical type surface roughness measuring apparatus is used in the step of measuring.
In present invention, there is prepared a representative wafer sampled or chosen from a wafer lot, the lot being a bunch of wafers sliced from the same silicon crystal ingot and initial surface height variation (recesses and projections) of the representative wafer is known previously. Prior to palanarizing the wafers of the entire lot, test etching is executed on the representative wafer in predetermined etching conditions, e.g. kinds of the activated species gas and added gasses, flow rate, power of microwave, etc. The surface height variation of the wafer is measured and an etching profile is derived from the measured data and the initial data. Thereby, there is achieved an effect of capable of reducing occurrence of failed products by nanotopography. Further, there is used the maximum pitch width p so far as nanotopography does not occur for each lot and therefore, there is achieved an effect of capable of meeting conflicting requests of nanotopography and calculation load.